In the rapidly advancing semiconductor manufacturing industry, complementary metal oxide semiconductor (CMOS) finFET devices are favored for many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios formed vertically with respect to a top surface of the substrate, and in which channel and source/drain regions of semiconductor transistor devices are formed. The fins are isolated, raised structures. A gate is formed over and along the sides of the fins, utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices.
FIG. 1A is an isometric view of a conventional finFET 100. The fins 105, 106 comprise raised oxide defined (OD) regions 105, 106 above a semiconductor substrate 101 (shown in FIGS. 1C, 1D). Fins 105, 106 are separated from each other by a shallow trench isolation (STI) region 102, and are located between a pair of STI regions 104. The fins 105, 106 have a step height 107 above the top surface of the STI regions 102. Polycrystalline silicon gate electrodes 108 are formed above the fins 105, 106. Sidewall spacers 110 are formed on both sides of each gate electrode 110, for forming lightly doped drain (LDD) implant regions (not shown).
FIG. 1B shows one of the fins 106 after an epitaxial growth step raises the surface 106e of the fin 106. The top portion 106e of the fin 106 acquires an approximately pentagonal shape, with lateral extensions 106L that extend in the direction of the top surface of the substrate 101 (shown in FIGS. 1C, 1D).
FIGS. 1C and 1D show the X-direction (front) and Y-direction (side) elevation views of the finFET 100 of FIG. 1A, after formation of the silicon oxide hard mask 112 and dummy side wall spacers 110, but before the epitaxial layer formation.
FIGS. 1E and 1F show the X-direction (front) and Y-direction (side) elevation views of the finFET 100 of FIG. 1A, after performing dual epitaxial processing. A photoresist (not shown) is deposited over the PMOS, and a first epitaxial process is performed on the NMOS fin 106, forming a Si, SiP, or SiC layer 106e over the fin 106 of the NMOS finFET. The PMOS is formed by a silicon recess process, in which the NMOS is masked by a photoresist (not shown), the silicon is etched from the PMOS dummy fin 105 and is replaced by SiGe, grown in the second epitaxial formation step. Thus, as shown in FIGS. 1E and 1F, the dummy fin 105 of the PMOS is replaced by a solid SiGe fin 124.
As shown in FIG. 1E, the epitaxial SiGe lateral extension 124L of PMOS fin 124 and lateral extension 106L of NMOS fin 106e extend laterally towards each other, reducing the window between adjacent fin side extensions.